Sharing the Limits

Aryeh Eiderman <>

1. The purpose

  There are many step&direction motion control designs that are based on an interface with limited input/output resources. For example, a PC parallel port or low pin count microcontrollers. In situations like these the usage of signal lines need to be multifunctional.
  The most common way to reduce the I/O signal count is the connection of inputs such as limits to the same line. They can be combined in parallel for normally open switch functionality and in series for normally closed switch functionality.
  A limitation of combined series or parallel switches is the need to have knowledge of the previous state, so if these inputs are active on initialization (such as power up) when the previous state is unknown, the system is non-functional and requires the assistance of a human operator.
  This limitation can be fixed by addition of the external circuits implementing the simple logic described below.

2. One wire limit

  Here I describe the way to get the information about the state of two limits (positive and negative) for single axis using only one signal line.
  In this implementation the corresponding limit switch is enabled according to the DIRECTION signal (DIR, CW/CCW) state: when DIRECTION signal is high (1) only the positive limit (LIM POS) state is significant, when DIRECTION signal is low (0) only the negative limit (LIM NEG) state is significant.
  The following circuit [Fig. 1] implements this logic using four two-input NAND gates (one standard 14-pin chip) and is compatible both for normally closed and normally open limit switches:

Fig. 1

  To determine which limit polarity is sensed when not moving, read the DIRECTION signal while the LIM signal is active (active means high (1) for normally closed or low (0) for normally open switch). If the DIRECTION signal is high, it's on the positive limit, if it's low it's on the negative limit. The state can be verified by inverting DIRECTION and testing the LIM signal to be active.
  In motion only one limit value has to be monitored as the controller defines the state of DIRECTION line.

3. The step is the limit

  Assuming that controller's output in high (1) state may also be used as input, we can reduce the dedicated limit lines to zero, without loosing the information, by sharing the result limit signal described above (LIM) with corresponding axis STEP (CLOCK) signal.
  Here we have to separate the STEP signal that comes from controller and STEP signal that goes to driver to provide different functionality depending on limit state: STEP signal that comes from controller in high (1) state goes to represent the limit, and the STEP signal that goes to the driver must remain unchanged when the limit is active (note that this scheme is good only for systems like the most of stepper motor based ones that are capable to make the immediate stop or any step-to-servo closed loop systems).
  The following circuit [Fig. 2] implements this logic using four two-input NAND gates (one standard 14-pin chip) with one transistor and requires the jumper setting for normally closed or normally open limits functionality:

Fig. 2

  The procedure for state determination is the same as for LIM above, except that the STEP line is going to be checked and only when it has the high (1) state set by controller and the active limit state is always low (0). Thus the native STEP operation mode here is active low (pulse produced as high-to-low -> delay -> low-to-high) - that ensures the correct determination in the idle mode.
  This circuit has an additional advantage as this logic provides an automatic protection against the over travel regardless the controller capabilities.

4. Conclusion

  The above circuits are a simple and inexpensive way to upgrade existing designs and to be implemented in new upcoming systems.

* My heartiest thanks to Phil Moore (, the editor of this article and my great hardware teacher.